Computer-based systems contain semiconductor devices, such as, for example, memory devices and processing devices. Memory is where information is stored while waiting to be operated on by the Central Processing Unit (CPU) of the computer. Memory is controlled by a memory controller, which can form part of the CPU or be separate from the CPU. The memory controller has an interface with the memory for communicating information. Known interfaces include parallel interfaces and serial interfaces.
Parallel interfaces use a large number of pins to read and write data. Unfortunately, as the number of input pins and wires increases, so do a number of undesired effects. These undesired effects include inter-symbol interference, signal skew and cross talk. Therefore, there is a need in the art for memory modules that have increased memory capacities and/or operating speeds while minimizing the number of input pins and wires for accessing the memory modules.
Serial interfaces use fewer pins to read and write data. Serial flash memory is now available, but this tends to be very slow. For example, many conventional memories are using serial bus interface schemes that operate in the range of 1 MHz-20 MHz with the SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) compatible interface. However, those serial interface standards are usually slower than their parallel counterparts.
With reference to FIGS. 1A, 1B, 1C and 1D, shown are four primary flash memory architectures. The four primary flash-memory architectures include a traditional XIP model as shown in FIG. 1A, a shadow model as shown in FIG. 1B, a store-and-download model with NAND as shown in FIG. 1C, and a newer store-and-download model with hybridized NAND flash memory as shown in FIG. 1D.
Referring to FIG. 1A, the traditional XIP model has a NOR flash memory 102 and volatile memory 103, which is likely SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), connected to an application processor 101. In the XIP model, the NOR flash memory 102 executes code, while the volatile memory 103 accounts for constantly changing system elements, such as variables, stack and heat. In the XIP model, the NOR flash memory 102 can also provide data and code storage as well. The advantage of the XIP model is simplicity, but the disadvantage is its slow write speed.
Referring to FIG. 1B, the shadow model has a NOR flash memory 105, NAND flash memory 106 and volatile memory 107, which is likely SRAM or DRAM, connected to an application processor 104. Users boot a system with the NOR flash memory 105 and use the NAND flash memory 106 for storage. The volatile memory 107 handles all of the execution. The shadow model is an expensive model in that it is using the NOR flash memory 105, which is relatively pricey, only to boot up the system. The architecture is also complex, which means that it consumes more design time and cost. The shadow model also tends to be power-hungry because the volatile memory is constantly active.
To overcome the space issue, which is a huge factor, for example, in mobile handheld devices, the store-and-download architecture is employed as shown in FIG. 1C. The store-and-download architecture has a NAND flash memory 110 and volatile memory 111, which is likely SRAM or DRAM, connected to an application processor 108. The store-and-download architecture has no NOR flash memory, but there is an OTP (one-time-programmable) storage 109 or ROM (Read Only Memory) core designed into the application processor 108. The application processor 108 loads information into the volatile memory 111, which accesses the NAND flash memory 110 for data storage. The architecture is complex and requires more initial engineering costs, but ultimately, the unit cost of the system is less expensive. The main difficulty of the model is that users must employ extensive error-correction and error-detection coding because NAND flash memory is typically less reliable. Storing and downloading designs tend to require more power, as the RAM takes a more active role.
Referring to FIG. 1D, the hybrid store and download model has a hybrid NAND flash memory 113 and volatile memory 114, which is likely SRAM or DRAM, connected to an application processor 112. The hybrid NAND flash memory 113 mixes SRAM, control logic and NAND flash memory to create a memory device that is supposed to look like a NOR flash device. This hybrid model reads much faster than a standard NAND flash device and at the same speed as a NOR flash device. It also achieves better write performance than NOR flash devices. Hybrid NAND flash memories are now available. Hybrid model requires less error-correction and error-detection coding than store-and-download models with standard NAND flash memories. The unit cost for hybridized NAND flash memories is, for example, 30 to 40% less than NOR flash memories at the same density. The cost of stand-alone NAND flash memories is slightly less than that of hybridized NAND flash memories.
The memory systems using any of the four primary flash memory architectures need much time for engineering design, software development and verification.